Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the designer describes a module in terms of signals that are generated and propagated through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
When ICs are designed at a higher level, lower level representations are needed before a design can be fabricated or implemented on hardware. For example, if a design is to be implemented on a programmable logic device (PLD), the process to translate the design into an executable form includes: synthesis, mapping, placement, routing, and bitstream generation. At each step, transformations occur which may introduce an error into the design. Design engineers generally utilize a wide range of tools enabling them to initially automate these steps and then modify, test, and debug at each level as needed to optimize performance and ensure correctness of the IC.
In order to verify that the circuit will behave as expected, simulations are conducted at the different stages of the design flow. The verification and debugging at the various stages can be complex, time consuming, and prone to human error, since the designer must manually track down the origin of any inconsistencies by tracing signal and state transitions at each level.
The present invention may address one or more of the above issues.